Evaluating Template-Based Instruction Compression on Transport Triggered Architectures

In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. Furthermore, code compression can decrease the power consumption of the chip. In this paper, a code compression method based on instruction templates has been used to improve the code density of transport triggered architecture. Six applications taken from different application domains are used for benchmarking. The obtained results show significant improvements in code density.